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http://www.farfield-group.com/Flip-Flop.aspOML cheap filp How do I make it a set

How do you convert it into a set dominant gated SR latch
Another weirdly worded question inside my digital logic book,
http://www.farfield-group.com/Flip-Flop.asp. It does not specifically define setdominant or resetdominant  nor should it show utilizing these in reality with drawing circuit diagrams. I've read and reread the chapters also it doesn't specify how to do that,
cheap filp.
I did some research online and apparently NOR SR latches are reset dominant and NAND SR latches are placed dominant,
flip flop shoe sale?
I understand that unpredictable behavior happens if S and R inputs are generally equal to 1 once the clock changes to a 0. Given a circuit,
flip flop, I'm likely to build a set dominant gated SR latch in which the conditions S=R=1 causes the latch to get set one.
I've included the circuit we're directed at focus on and my work for balance so that it is set dominant (don't judge me lol).
A reset dominant sr latch is often a latch with two data inputs, S and R which includes an excitation table similar to an SR latch, except that when both S and R are 1, another output must be 0 (reset). Set dominant is scheduled similarly: the subsequent output when S and R tend to be 1 needs to be 1 (set).
And that means you should alter the characteristic table so that the "X" over the last row could be the proper value ("1" since you've been called for a "setdominant" SR latch) and after that use whatever plugnchug method you have been given to turn a characteristic table in to a working circuit.
A attempt fails since it gives an undefined nextstate when R=S=0, plus enters an undefined state whenever clk is low.
(BTW: AFAIK "Set/Reset dominant" is just not standard terminology that could be defined in the text book, it's only a madeup good name for the purpose of this specific problem.)Related articles:

  
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